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? 1999, 2000 data sheet description the pd780021a, 780022a, 780023a, and 780024a are members of the pd780024a subseries of the 78k/0 series. only selected functions of the existing pd78054 subseries are provided, and the serial interface is enhanced. the pd780021ay, 780022ay, 780023ay, and 780024ay are the pd780024a subseries with a multimaster supporting i 2 c bus interface, which makes them suitable for av equipment. flash memory versions, the pd78f0034a and 78f0034ay, that can operate in the same power supply voltage range as the mask rom versions, and various development tools, are also supported. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. pd780024a, 780034a, 780024ay, 780034ay subseries user? manual: u14046e 78k/0 series user? manual instructions: u12326e features internal rom and ram item program memory data memory package part number (internal rom) (internal high-speed ram) pd780021a, 780021ay 8 kb 512 bytes ? 64-pin plastic sdip (19.05mm (750)) pd780022a, 780022ay 16 kb ? 64-pin plastic qfp (14 14) pd780023a, 780023ay 24 kb 1024 bytes ? 64-pin plastic tqfp (12 12) pd780024a, 780024ay 32 kb external memory expansion space: 64 kb minimum instruction execution time: 0.24 s (@ fx = 8.38 mhz operation) i/o ports: 51 (n-ch open-drain 5 v withstand voltage: 4) 8-bit resolution a/d converter: 8 channels (av dd = 1.8 to 5.5 v) serial interface: 3 channels pd780021a, 780022a, 780023a, 780024a: uart mode, 3-wire serial i/o mode (2 channels) pd780021ay, 780022ay, 780023ay, 780024ay: uart mode, 3-wire serial i/o mode, i 2 c bus mode timer: 5 channels power supply voltage: v dd = 1.8 to 5.5 v applications telephones, household electrical appliances, pagers, av equipment, car audios, office automation equipment, etc. 8-bit single-chip microcontrollers mos integrated circuit pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points. document no. u14042ej3v0ds00 (3rd edition) date published december 2000 n cp(k) printed in japan
2 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds ordering information part number package pd780021acw- 64-pin plastic sdip (19.05 mm (750)) pd780021agc- -ab8 64-pin plastic qfp (14 14) pd780021agk- -9et 64-pin plastic tqfp (12 12) pd780022acw- 64-pin plastic sdip (19.05 mm (750)) pd780022agc- -ab8 64-pin plastic qfp (14 14) pd780022agk- -9et 64-pin plastic tqfp (12 12) pd780023acw- 64-pin plastic sdip (19.05 mm (750)) pd780023agc- -ab8 64-pin plastic qfp (14 14) pd780023agk- -9et 64-pin plastic tqfp (12 12) pd780024acw- 64-pin plastic sdip (19.05 mm (750)) pd780024agc- -ab8 64-pin plastic qfp (14 14) pd780024agk- -9et 64-pin plastic tqfp (12 12) pd780021aycw- 64-pin plastic sdip (19.05 mm (750)) pd780021aygc- -ab8 64-pin plastic qfp (14 14) pd780021aygk- -9et 64-pin plastic tqfp (12 12) pd780022aycw- 64-pin plastic sdip (19.05 mm (750)) pd780022aygc- -ab8 64-pin plastic qfp (14 14) pd780022aygk- -9et 64-pin plastic tqfp (12 12) pd780023aycw- 64-pin plastic sdip (19.05 mm (750)) pd780023aygc- -ab8 64-pin plastic qfp (14 14) pd780023aygk- -9et 64-pin plastic tqfp (12 12) pd780024aycw- 64-pin plastic sdip (19.05 mm (750)) pd780024aygc- -ab8 64-pin plastic qfp (14 14) pd780024aygk- -9et 64-pin plastic tqfp (12 12) remark indicates rom code suffix.
3 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are same. pd78054 with added iebus tm controller. emi-noise reduced. 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with added uart and d/a converter and enhanced i/o pd780034a pd780988 pd780034ay 64-pin ram capacity of the pd780024a increased pd780024a with enhanced a/d converter on-chip inverter controller and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and increased rom, ram capacity emi-noise reduced version of the pd78064 basic subseries for lcd drive, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42-/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin pd78054 with enhanced serial i/o 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. pd78054 with added timer and enhanced external interface rom-less version of the pd78078 100-pin pd78078y with enhanced serial i/o and limited function 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780824 for automobile meter driver. on-chip d-can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin pd780701y on-chip d-can/iebus controller 80-pin pd780833y on-chip controller compliant with j1850 (class 2) pd780948 on-chip d-can controller 64-pin pd780078 pd780078y pd780034a with added timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd and c/d. display output total: 53 pd78044f with added n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for vfd drive. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338
4 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds the major functional differences between the subseries are listed below. non y subseries function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3ch (time division uart: 1ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1ch 1ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1ch 8ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780338 48 k to 60 k 3 ch 2ch 1ch 1ch 10 ch 1 ch 2 ch (uart: 2 ch) 54 1.8 v drive pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v pd780824 32 k to 60 k 2 ch (uart: 1 ch) 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel dash board control bus interface supported
5 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds y subseries function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control pd78078y 48 k to 60 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1ch, 88 1.8 v pd78070ay i 2 c: 1 ch) 61 2.7 v pd780018ay 48 k to 60 k 3 ch (i 2 c 1 ch) 88 pd780058y 24 k to 60 k 2 ch 2 ch 3 ch (time division 68 1.8 v uart: 1 ch, i 2 c: 1 ch) pd78058fy 48 k to 60 k 3 ch (uart: 1 ch, 69 2.7 v pd78054y 16 k to 60 k i 2 c: 1 ch) 2.0 v pd780078y 48 k to 60 k 2 ch 8 ch 4 ch (uart: 2 ch, 52 1.8 v i 2 c: 1 ch) pd780034ay 8 k to 32 k 1 ch 3 ch (uart: 1 ch, 51 pd780024ay 8 ch i 2 c: 1 ch) pd78018fy 8 k to 60 k 2 ch (i 2 c: 1 ch) 53 lcd pd780308y 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 3 ch (time division 57 2.0 v drive uart: 1 ch, i 2 c: 1 ch) pd78064y 16 k to 32 k 2 ch (uart: 1 ch, i 2 c: 1 ch) for bus pd780701y 60 k 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, 67 3.5 v interface pd780833y i 2 c: 1 ch) 65 4.5 v remark the functions of non y subseries and y subseries products are the same, except for the serial interface.
6 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds overview of functions part number pd780021a pd780022a pd780023a pd780024a item pd780021ay pd780022ay pd780023ay pd780024ay internal rom 8 kb 16 kb 24 kb 32 kb memory high-speed ram 512 bytes 1024 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution on-chip minimum instruction execution time cycle variable function when main system 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 mhz operation) clock selected when subsystem 122 s (@ 32.768 khz operation) clock selected instruction set ?16-bit operation ?multiply/divide (8 bits 8 bits,16 bits 8 bits) ?bit manipulation (set, reset, test, boolean operation) ?bcd adjust, etc. i/o ports total: 51 ?cmos input: 8 ?cmos i/o: 39 ?n-ch open-drain i/o (5-v withstand voltage): 4 a/d converter ?8-bit resolution x 8 channels ?low-voltage operation available: av dd = 1.8 to 5.5 v serial interface ? pd780021a, 780022a, 780023a, 780024a uart mode: 1 channel 3-wire serial i/o mode: 2 channels ? pd780021ay, 780022ay, 780023ay, 780024ay uart mode: 1 channel 3-wire serial i/o mode: 1 channel i 2 c bus mode (multimaster supporting): 1 channel timers ?16-bit timer/event counter: 1 channel ?8-bit timer/event counter: 2 channels ?watch timer: 1 channel ?watchdog timer: 1 channel timer outputs 3 (8-bit pwm output capable: 2) clock output ?65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (@ 8.38 mhz operation with main system clock ) ?32.768 khz (@ 32.768 khz operation with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (@ 8.38 mhz operation with main system clock) vectored maskable internal: 13, external: 5 interrupt non-maskable internal: 1 sources software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ?0 to +85 c package ?64-pin plastic sdip (19.05 mm (750)) ?64-pin plastic qfp (14 14) ?64-pin plastic tqfp (12 12) time
7 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds contents 1. pin configuration (top view) ................................................................................................... 8 2. block diagram ............................................................................................................................. 11 3. pin functions ............................................................................................................................... .12 3.1 port pins ............................................................................................................................... ..................... 12 3.2 non-port pins ............................................................................................................................... ............. 13 3.3 pin i/o circuits and recommended connection of unused pins ..................................................... 15 4. memory space ............................................................................................................................... 17 5. peripheral hardware function features .......................................................................18 5.1 ports ............................................................................................................................... ............................ 18 5.2 clock generator ............................................................................................................................... ......... 19 5.3 timer/counter ............................................................................................................................... ............ 20 5.4 clock output/buzzer output controller ................................................................................................ 24 5.5 a/d converter ............................................................................................................................... ............ 25 5.6 serial interface ............................................................................................................................... ........... 26 6. interrupt functions .................................................................................................................29 7. external device expansion function ...............................................................................32 8. standby function .......................................................................................................................32 9. reset function ............................................................................................................................32 10. mask option ............................................................................................................................... ....32 11. instruction set ...........................................................................................................................33 12. electrical specifications ......................................................................................................35 13. package drawings .....................................................................................................................57 14. recommended soldering conditions ................................................................................60 appendix a. development tools ................................................................................................62 appendix b. related documents ................................................................................................65
8 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 1. pin configuration (top view) 64-pin plastic sdip (19.05 mm (750)) pd780021acw- , 780022acw- , 780023acw- , 780024acw- pd780021aycw- , 780022aycw- , 780023aycw- , 780024aycw- notes 1. sda0 and scl0 are incorporated only in the pd780024ay subseries. 2. si31, so31, and sck31 are incorporated only in the pd780024a subseries. cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when the pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, and 780024ay are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic xt1 xt2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 note1 p33/scl0 note1 p34/si31 note2 p35/so31 note2 p36/sck31 note2 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1
9 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 64-pin plastic qfp (14 14) pd780021agc- -ab8, 780022agc -ab8, 780023agc- -ab8, 780024agc- -ab8, pd780021aygc- -ab8, 780022aygc -ab8, 780023aygc- -ab8, 780024aygc- -ab8 64-pin plastic tqfp (12 12) pd780021agk- -9et, 780022agk -9et, 780023agk- -9et, 780024agk- -9et, pd780021aygk- -9et, 780022aygk -9et, 780023aygk- -9et, 780024aygk- -9et notes 1. sda0 and scl0 are incorporated only in the pd780024ay subseries. 2. si31, so31, and sck31 are incorporated only in the pd780024a subseries. cautions 1. connect the ic (internally connected) pin directory to v sso or v ss1 . 2. connect the av ss pin to v ss0 . remark when the pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, and 780024ay are used in applications where the noise aygenerated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 note1 p33/scl0 note1 p34/si31 note2 p35/so31 note2 p36/sck31 note2 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic xt1 xt2 reset av dd av ref p10/ani0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50
10 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds p64 to p67: port 6 p70 to p75: port 7 pcl: programmable clock rd: read strobe reset: reset rxd0: receive data sck30, sck31, scl0: serial clock sda0: serial data si30, si31: serial input so30, so31: serial output ti00, ti01, ti50, ti51: timer input to0, to50, to51: timer output txd0: transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input asck0: asynchronous serial clock astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground buz: buzzer clock ic: internally connected intp0 to intp3: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p25: port 2 p30 to p36: port 3 p40 to p47: port 4 p50 to p57: port 5
11 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 2. block diagram notes 1. incorporated only in the pd780024a subseries. 2. incorporated only in the pd780024ay subseries. remark the internal rom and ram capacities vary depending on the product. ti00/to0/p70 16-bit timer/ event counter serial interface 30 interrupt control buzzer output clock output control 78k/0 cpu core port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 p70 to p75 p64 to p67 p50 to p57 p40 to p47 p30 to p36 p20 to p25 p10 to p17 p00 to p03 external access system control reset x1 x2 xt1 xt2 rd/p64 wr/p65 wait/p66 astb/p67 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rom ram a/d converter uart0 v dd0 v dd1 v ss0 v ss1 ic watchdog timer watch timer 8-bit timer/ event counter 50 8-bit timer/ event counter 51 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref buz/p75 pcl/p74 ani0/p10 to ani7/p17 intp0/p00 to intp3/p03 ti01/p71 serial interface 31 note1 si31/p34 so31/p35 sck31/p36 sda0/p32 i 2 c bus note2 scl0/p33
12 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 3. pin functions 3.1 port pins (1/2) pin name i/o function after alternate reset function p00 to p02 i/o port 0 input intp0 to 4-bit i/o port intp2 p03 input/output can be specified in 1-bit units. intp3/adtrg an on-chip pull-up resistor can be connected by means of software. p10 to p17 input port 1 input ani0 to ani7 8-bit input only port p20 i/o port 2 input si30 p21 6-bit i/o port so30 p22 input/output can be specified in 1-bit units. sck30 p23 an on-chip pull-up resistor can be connected by means of software. rxd0 p24 txd0 p25 asck0 p30 i/o port 3 n-ch open-drain i/o port input p31 7-bit i/o port an on-chip pull-up resistor can be p32 input/output can be specified in specified by the mask option. sda0 note 1 p33 1-bit units. leds can be driven directly. scl0 note 1 p34 an on-chip pull-up resistor can be si31 note 2 p35 connected by means of software. so31 note 2 p36 sck31 note 2 p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. the interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. p64 i/o port 6 input rd p65 4-bit i/o port wr p66 input/output can be specified in 1-bit units. wait p67 an on-chip pull-up resistor can be connected by means of software. astb notes 1. sda0 and scl0 are incorporated only in the pd780024ay subseries. 2. si31, so31, and sck31 are incorporated only in the pd780024a subseries.
13 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 3.1 port pins (2/2) pin name i/o function after alternate reset function p70 i/o port 7 input ti00/to0 p71 6-bit i/o port ti01 p72 input/output can be specified in 1-bit units. ti50/to50 p73 an on-chip pull-up resistor can be connected by means of software. ti51/to51 p74 pcl p75 buz 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 input external interrupt request input for which the valid edge (rising edge, input p00 intp2 falling edge, or both rising and falling edges) can be specified p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 si31 note 1 p34 so30 output serial interface serial data output input p21 so31 note 1 p35 sda0 note 2 i/o serial interface serial data input/output input p32 sck30 i/o serial interface serial clock input/output input p22 sck31 note 1 p36 scl0 note 2 p33 rxd0 input serial data input for asynchronous serial interface input p23 txd0 output serial data output for asynchronous serial interface input p24 asck0 input serial clock input for asynchronous serial interface input p25 ti00 input external count clock input to 16-bit timer/event counter 0 input p70/to0 capture trigger input to capture register 01 (cr01) of 16-bit timer/event counter 0 ti01 capture trigger input to capture register 00 (cr00) of 16-bit timer/event counter 0 p71 ti50 external count clock input to 8-bit timer/event counter 50 p72/to50 ti51 external count clock input to 8-bit timer/event counter 51 p73/to51 to0 output 16-bit timer/event counter 0 output input p70/ti00 to50 8-bit timer/event counter 50 output (also used for 8-bit pwm output) input p72/ti50 to51 8-bit timer/event counter 51 output (also used for 8-bit pwm output) p73/ti51 pcl output clock output (for trimming of main system clock and subsystem clock) input p74 buz output buzzer output input p75 ad0 to ad7 i/o lower address/data bus for expanding memory externally input p40 to p47 a8 to a15 output higher address bus for expanding memory externally input p50 to p57 rd output strobe signal output for reading from external memory input p64 wr strobe signal output for writing to external memory p65 wait input wait insertion at external memory access input p66 astb output strobe output that externally latches address information output to input p67 ports 4 and 5 to access external memory notes 1. si31, so31, sck31 are incorporated only in the pd780024a subseries. 2. sda0 and scl0 are incorporated only in the pd780024ay subseries.
14 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 3.2 non-port pins (2/2) pin name i/o function after alternate reset function ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input av dd a/d converter analog power supply. set potential to that of v dd0 or v dd1 av ss a/d converter ground potential. set potential to that of v ss0 or v ss1 reset input system reset input x1 input connecting crystal resonator for main system clock oscillation x2 xt1 input connecting crystal resonator for subsystem clock oscillation xt2 v dd0 positive power supply for ports v ss0 ground potential of ports v dd1 positive power supply (except ports) v ss1 ground potential (except ports) ic internally connected. connect directly to v ss0 or v ss1 .
15 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. types of pin i/o circuits pin name i/o i/o recommended connection of unused pins circuit type p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 via a resistor. p03/intp3/adtrg output: leave open. p10/ani0 to p17/ani7 25 input connect to v dd0 or v ss0 via a resistor. p20/s130 8-c i/o input: independently connect to v dd0 or v ss0 via a resistor. p21/so30 5-h output: leave open. p22/sck30 8-c p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q i/o input: independently connect to v dd0 via resistor. p32, p33 13-s output: leave open. ( pd780024a subseries only) p32/sda0 13-r ( pd780024ay subseries only) p33/scl0 ( pd780024ay subseries only) p34/si31 note 8-c input: independently connect to v dd0 or v ss0 via a resistor. p35/so31 note 5-h output: leave open. p36/sck31 note 8-c p40/ad0 to p47/ad7 5-h i/o input: independently connect to v dd0 via a resistor. output: leave open. p50/a8 to p57/a15 i/o input: independently connect to v dd0 or v ss0 via a resistor. p64/rd i/o output: leave open. p65/wr p66/wait p67/astb p70/ti00/to0 8-c p71/ti01 p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input xt1 16 connect to v dd0 . xt2 leave open. av dd connect to v dd0 or v dd1 . av ref connect to v ss0 or v ss1 . av ss ic connect directly to v ss0 or v ss1 . note si31, so31, and sck31 are incorporated only in the pd780024a subseries.
16 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds figure 3-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 8-c type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pull-up enable type 13-q type 13-r data output disable in/out n-ch v dd0 mask option ? ? ? ? ? ? p-ch n-ch v ref (threshold voltage) v ss0 in data output disable in/out n-ch v ss0 type 25 data output disable in/out n-ch v ss0 v dd0 mask option ? ? ? ? ? ?
17 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 4. memory space figure 4-1 shows the memory map of the figure 4-1. memory map note the internal rom and internal high-speed ram capacities vary depending on the products (see the following table). part number last address of internal rom start address of internal high-speed ram nnnnh mmmmh note reserved external memory internal rom note data memory space program memory space ffffh ff00h feffh fee0h fedfh mmmmh mmmmh 1 f7ffh nnnnh + 1 nnnnh 0000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h f800h
18 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. cmos input (port 1): 8 cmos i/o (ports 0, 2, 4 to 7, p34 to p36): 39 n-channel open-drain i/o (p30 to p33): 4 total: 51 table 5-1. port functions name pin name function port 0 p00 to p03 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. port 1 p10 to p17 input-only port. port 2 p20 to p25 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. port 3 p30 to p33 n-channel open-drain i/o port. input/output can be specified in 1-bit units. a pull-up resistor can be specified by mask option. leds can be driven directly. p34 to p36 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. port 4 p40 to p47 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. the interrupt request flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. leds can be driven directly. port 6 p64 to p67 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software. port 7 p70 to p75 i/o port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by means of software.
19 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 5.2 clock generator a system clock generator is incorporated. the minimum instruction execution time can be changed. 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 mhz operation with main system clock) 122 s (@ 32.768 khz operation with subsystem clock) figure 5-1. clock generator block diagram xt1 xt2 x1 x2 f xt f x subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller 2 f x 2 2 f x 2 3 f x 2 4 f x f xt 2 prescaler selector stop 2 1
20 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 5.3 timer/counter five timer/counter channels are incorporated. 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel table 5-2. operations of timer/event counter 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter 0 event counters 50, 51 operation mode interval timer 1 channel 2 channels 1 channel note 1 1 channel note 2 external event counter 1 channel 2 channels function timer outputs 1 2 ppg outputs 1 pwm output 2 pulse width measurement 2 inputs square wave outputs 1 2 interrupt sources 2 2 2 1 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.
21 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds figure 5-2. block diagram of 16-bit timer/event counter 0 internal bus ti01/p71 f x f x /2 2 f x /2 6 f x /2 3 ti00/to0/p70 16-bit capture/compare register 01 (cr01) match match 16-bit timer counter 0 (tm0) clear noise elimi- nator inttm00 to0/ti00/p70 inttm01 internal bus selector 16-bit capture/compare register 00 (cr00) selector selector selector noise elimi- nator noise elimi- nator output controller
22 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds figure 5-3. block diagram of 8-bit timer/event counter 50 figure 5-4. block diagram of 8-bit timer/event counter 51 internal bus 8-bit compare register 50 (cr50) ti50/to50/p72 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 level inversion timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p72 selector 8-bit timer counter 50 (tm50) selector internal bus ti51/to51/p73 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 level inversion timer mode control register 51 (tmc51) s r q r inv selector inttm51 to51/ti51/p73 selector selector selector 8-bit compare register 51 (cr51) 8-bit timer counter51 (tm51) s
23 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds figure 5-5. watch timer block diagram figure 5-6. watchdog timer block diagram f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector selector oscillation stabilization time selection register (osts) clock input controller intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 internal bus divider divided clock selector output controller division mode selector run wdtm4 wdtm3 watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) run f x /2 8 f x
24 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 5.4 clock output/buzzer output controller a clock output/buzzer output controller (cku) is incorporated. clocks with the following frequencies can be output as clock output. 65.5 khz/131 khz/262 khz/524 khz/1.05 mhz/2.10 mhz/4.19 mhz/8.38 mhz (@ 8.38 mhz operation with main system clock) 32.768 khz (@ 32.768 khz operation with subsystem clock) clocks with the following frequencies can be output as buzzer output. 1.02 khz/2.05 khz/4.10 khz/8.19 khz (@ 8.38 mhz operation with main system clock) figure 5-7. block diagram of clock output/buzzer output control circuit cku prescaler f x f xt 8 clock controller pcl/p74 buz/p75 4 f x to f x /2 7 f x /2 10 to f x /2 13 selector bcs0, bcs1 bzoe cloe bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 internal bus clock output selection register (cks) selector
25 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 5.5 a/d converter an a/d converter consisting of eight 8-bit resolution channels is incorporated. the following two a/d conversion operation startup methods are available. hardware start software start figure 5-8. a/d converter block diagram tap selector intad av dd intp3 internal bus av ref a/d conversion result register (adcr0) controller succesive approximation register (sar) edge detector ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/adtrg/p03 selector sample & hold circuit voltage comparator series resistor string edge detector av ss
26 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 5.6 serial interface three serial interface channels are incorporated. pd780024a subseries serial interface uart0: 1 channel serial interface 30, 31: 2 channels pd780024ay subseries serial interface uart0: 1 channel serial interface 30: 1 channel serial interface iic0 1 channel (1) serial interface uart0 serial interface uart0 has two modes: asynchronous serial interface (uart) mode and infrared data transfer mode. asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted and received. the on-chip uart-dedicated baud-rate generator enables communication using a wide range of selectable baud rates. in addition, a baud rate can be also defined by dividing the clock input to the asck0 pin. the uart-dedicated baud-rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). infrared data transfer mode this mode enables pulse output and pulse reception in data format. this mode can be used for office equipment applications such as personal computers. figure 5-9. block diagram of serial interface uart0 internal bus receive buffer register0 rxb0 rxd0/p23 txd0/p24 receive shift register0 pe0 fe0 ove0 asynchronous serial interface status register0 (asis0) txs0 intser0 intst0 baud rate generator f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register0 (asim0) intsr0 receive controller (parity check) transmit shift register0 transmit controller (parity addition) rx0 p25/asck0
27 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds (2) serial interface 3n note serial interface 3n has one mode: 3-wire serial i/o mode. 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3n), serial output line (so3n), and serial input line (si3n). since simultaneous transmit and receive operations are enabled in the 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in 8-bit data in the serial transfer is fixed as msb. the 3-wire serial i/o mode is useful for connection to a peripheral i/o devices, and display controllers, etc., that include a clocked serial interface. figure 5-10. block diagram of serial interface 3n remark pd780024a subseries: n = 0, 1 pd780024ay subseries: n = 0 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 3n (sio3n) si3n so3n sck3n intcsi3n f x /2 3 f x /2 4 f x /2 5
28 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds (3) serial interface iic0 ( pd780024ay subseries only) serial interface iic0 has one mode: i 2 c (inter ic) bus mode (supporting multimaster). ? 2 c bus mode (supporting multimaster) this is an 8-bit data transfer mode using two lines: a serial clock line (scl0) and a serial data bus line (sda0). this mode complies with the i 2 c bus format, and can output a ?tart condition? ?ata? and a ?top condition during transmission via the serial data bus. this data is automatically detected by hardware during reception. since scl0 and sda0 are open-drain outputs in iic0, pull-up resistors for the serial clock line and the serial data bus line are required. figure 5-11. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator matched signal iic shift register 0 (iic0) so0 latch iice0 d set clear cl00 sda0/p32 scl0/p33 n-ch open- drain output data hold time corrector acknowledge detector wake-up controller acknowledge detector stop condition detector serial clock counter interrupt request signal generator serial clock controller n-ch open-drain output serial clock wait controller prescaler intiic0 f x cld0 iic transfer clock select register 0 (iiccl0) internal bus lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector dad0 smc0 dfc0 cl00
29 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 6. interrupt functions a total of 20 interrupt sources are provided, divided into the following three types. non-maskable: 1 maskable: 18 software: 1 table 6-1. interrupt source list interrupt default interrupt source internal/ type priority note 1 name trigger external non- intwdt watchdog timer overflow internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 serial interface uart0 reception error internal 000eh (b) generation 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi30 end of serial interface 30 transfer 0014h 9 intcsi31 end of serial interface 31 transfer 0016h [only for pd780024a subseries] 10 intiic0 end of serial interface iic0 transfer 0018h [only for pd780024ay subseries] 11 intwti reference time interval signal from watch timer 001ah 12 inttm00 match between tm0 and cr00 001ch (when cr00 is specified as compare register) detection of ti01 valid edge (when cr00 is specified as capture register) 13 inttm01 match between tm0 and cr01 001eh (when cr01 is specified as compare register) detection of ti00 valid edge (when cr01 is specified as capture register) 14 inttm50 match between tm50 and cr50 0020h 15 inttm51 match between tm51 and cr51 0022h 16 intad0 end of a/d conversion 0024h 17 intwt watch timer overflow 0026h 18 intkr port 4 falling edge detection external 0028h (d) software brk brk instruction execution 003eh (e) notes 1. the default priority is the priority when several maskable interrupt requests are generated at the same time. 0 is the highest order, and 18 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1. remark two watchdog timer interrupt sources (intwdt): a non-maskable interrupt and a maskable interrupt (internal), are available, either of which can be selected. basic configuration type note 2 vector table address
30 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) internal bus priority controller vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority controller vector table address generator standby release signal interrupt request mk ie pr isp if priority controller vector table address generator external interrupt edge enable register (egp, egn) edge detector internal bus standby release signal interrupt request
31 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds figure 6-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mk ie pr isp if priority controller vector table address generator falling edge detector internal bus standby release signal interrupt request priority controller vector table address generator internal bus interrupt request
32 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 7. external device expansion function the external device expansion function is for connecting external devices to areas other than the internal rom, ram, and sfr. ports 4 to 6 are used for external device connection. 8. standby function the following two standby modes are available for further reduction of system current consumption. halt mode: in this mode, the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. stop mode: in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. this can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped). figure 8-1. standby function note the current consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) of the processor clock control register (pcc). the stop instruction cannot be used. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 9. reset function the following two reset methods are available. external reset by reset signal input internal reset by watchdog timer runaway time detection 10. mask option table 10.1 pin mask option selection subseries name pins mask option pd780024a subseries p30 to p33 an on-chip pull-up resistor can be specified in 1-bit units. pd780024ay subseries p30 and p33 the mask option can be used to specify the connection of an on-chip pull-up resistor to p30 to p33 note , in 1-bit units. note the pd780024ay subseries has p30 and p31 only. main system clock operation stop mode main system clock operation is stopped interrupt request interrupt request halt instruction halt instruction interrupt request stop instruction css = 1 css = 0 subsystem clock operation note halt mode halt mode note clock supply for cpu is stopped, oscillation is maintained clock supply for cpu is stopped, oscillation is maintained
33 pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data sheet u14042ej3v0ds 11. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a 2nd operand 1st operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
34 data sheet u14042ej3v0ds (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 2nd operand 1st operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz
35 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v av dd ?.3 to v dd + 0.3 note v av ref ?.3 to v dd + 0.3 note v av ss ?.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, p40 to p47, ?.3 to v dd + 0.3 note v p50 to p57, p64 to p67, p70 to p75, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open-drain without pull-up resistor ?.3 to + 6.5 v with pull-up resistor ?.3 to v dd + 0.3 note v output voltage v o ?.3 to v dd + 0.3 note v analog input voltage v an p10 to p17 analog input pin av ss ?0.3 to av ref0 + 0.3 note v and ?.3 to v dd + 0.3 note output current, i oh per pin ?0 ma high total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, p70 to p75 ?5 ma total for p20 to p25, p30 to p36 ?5 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to 20 ma low p36, p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, 50 ma p64 to p67, p70 to p75 total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a ?0 to +85 c temperature storage t stg ?5 to +150 c temperature note 6.5 v or below caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
36 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation v dd = 4.0 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation v dd = 4.0 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 oscillation v dd = 4.0 to 5.5 v 10 ms stabilization time note 2 30 external x1 input v dd = 4.0 to 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 1.0 5.0 x1 input v dd = 4.0 to 5.5 v 50 500 ns high-/low-level width 85 500 (t xh , t xl ) capacitance (t a = 25 c , v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75 p30 to p33 20 pf remark unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins. main system clock oscillator characteristics (t a = ?0 to 85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. c2 x1 x2 ic c1 c2 x1 x2 ic c1 x2 x1 pd74hcu04
37 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz v dd = 4.0 to 5.5 v recommended circuit 515 subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. c3 xt2 xt1 ic r c4 xt1 xt2
38 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay recommended oscillator constant main system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csb1000j 1.00 100 100 1.8 5.5 co., ltd. csa2.00mg040 2.00 100 100 1.8 5.5 cst2.00mg040 2.00 on-chip on-chip 1.8 5.5 csa3.58mg 3.58 30 30 1.8 5.5 cst3.58mgw 3.58 on-chip on-chip 1.8 5.5 csa4.19mg 4.19 30 30 1.8 5.5 cst4.19mgw 4.19 on-chip on-chip 1.8 5.5 csa5.00mg 5.00 30 30 1.8 5.5 cst5.00mgw 5.00 on-chip on-chip 1.8 5.5 csa8.00mtz 8.00 30 30 4.0 5.5 cst8.00mtw 8.00 on-chip on-chip 4.0 5.5 csa8.00mtz093 8.00 30 30 4.0 5.5 cst8.00mtw093 8.00 on-chip on-chip 4.0 5.5 csa8.38mtz 8.38 30 30 4.0 5.5 cst8.38mtw 8.38 on-chip on-chip 4.0 5.5 csa8.38mtz093 8.38 30 30 4.0 5.5 cst8.38mtw093 8.38 on-chip on-chip 4.0 5.5 tdk ccr3.58mc3 3.58 on-chip on-chip 1.8 5.5 ccr4.19mc3 4.19 on-chip on-chip 1.8 5.5 ccr5.0mc3 5.00 on-chip on-chip 1.8 5.5 ccr8.0mc5 8.00 on-chip on-chip 2.0 5.5 ccr8.38mc5 8.38 on-chip on-chip 2.0 5.5 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, contact directly the manufacturer of the resonator used.
39 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, i oh per pin 1ma high all pins 15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, p35, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 0.8v dd v dd v p64 to p67, p74, p75 v ih2 p00 to p03, p20, p22, p23, p25, v dd = 2.7 to 5.5 v 0.8v dd v dd v p34, p36, p70 to p73, reset 0.85v dd v dd v v ih3 p30 to p33 v dd = 2.7 to 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 0.8v dd 5.5 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd 0.5 v dd v v dd 0.2 v dd v v ih5 xt1, xt2 v dd = 4.0 to 5.5 v 0.8v dd v dd v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, p35, v dd = 2.7 to 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 0 0.2v dd v p64 to p67, p74, p75 v il2 p00 to p03, p20, p22, p23, p25, v dd = 2.7 to 5.5 v 0 0.2v dd v p34, p36, p70 to p73, reset 0 0.15v dd v v il3 p30 to p33 4.0 v < < = 1 ma v dd 1.0 v dd v high i oh = 100 0.5 v dd v output voltage, v ol1 p30 to p33 v dd = 4.0 to 5.5 v, 2.0 v low p50 to p57 i ol = 15 ma 0.4 2.0 v p00 to p03, p20 to p25, p34 to p36, v dd = 4.0 to 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75 i ol = 1.6 ma v ol2 i ol = 400 remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
40 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p60 to p67, p70 to p75, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 note 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, ? a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lil2 x1, x2, xt1, xt2 ?0 a i lil3 p30 to p33 note1 ? a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v 3 a current, low mask option r 1 v in = 0 v, 15 30 90 k ? pull-up resistance p30, p31, p32 note2 , p33 note2 software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75 notes 1. pd780021a, 780022a, 780023a, 780024a: when pull-up resistors are not connected to p30 to p33 (specified by the mask option). pd780021ay, 780022ay, 780023ay, 780024ay: when pull-up resistors are not connected to p30 and p31 (specified by the mask option). 2. only for the pd780021a, 780022a, 780023a, and 780024a. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
41 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit power supply i dd1 8.38 mhz v dd = 5.0 v 10% note 2 when a/d converter is 5.5 11 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 6.5 13 ma operating 5.00 mhz v dd = 3.0 v 10% note 2 when a/d converter is 2 4 ma crystal oscillation stopped operating mode when a/d converter is 3 6 ma operating v dd = 2.0 v 10% note 3 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating i dd2 8.38 mhz v dd = 5.0 v 10% note 2 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating 5.00 mhz v dd = 3.0 v 10% note 2 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 3 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 4 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 4 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 xt1 = v dd stop mode v dd = 5.0 v 10% 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ), including the peripheral operation current (except the current through pull-up resistors of ports and the av ref pin). 2. when the processor clock control register (pcc) is set to 00h. 3. when pcc is set to 02h. 4. when main system clock operation is stopped.
42 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with 0.24 16 note 1 122 125 v dd 5.5 v 2/f sam +0.1 note2 v dd < 4.0 v 2/f sam +0.2 note2 note2 notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, the value becomes f sam = f x /8. 4.0 v <
43 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay t cy vs. v dd (main system clock operation) 16.0 5.0 1.0 2.0 1.6 0.4 0.24 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 operation guaranteed range
44 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay (2) read/write operation (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy 54 ns t add2 (3 + 2n)t cy 60 ns address output time from rd 87 ns t rdd2 (3 + 2n)t cy 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 33 ns t rdl2 (2.5 + 2n)t cy 33 ns input time from rd 43 ns t rdwt2 t cy 43 ns input time from wr 25 ns wait low-level width t wtl (0.5 + n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy 15 ns delay time from astb 15 ns delay time from t rdast 0.8t cy 15 1.2t cy ns rd 15 1.2t cy + 30 ns rd 15 1.2t cy + 30 ns delay time from wait remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.) (1/3)
45 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay (2) read/write operation (t a = ?0 to +85 c, v dd = 2.7 to 4.0 v) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy 108 ns t add2 (3 + 2n)t cy 120 ns output time from rd 148 ns t rdd2 (3 + 2n)t cy 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 40 ns t rdl2 (2.5 + 2n)t cy 40 ns input time from rd 75 ns t rdwt2 t cy 60 ns input time from wr 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy 30 ns delay time from astb 30 ns delay time from t rdast 0.8t cy 30 1.2t cy ns rd 30 1.2t cy + 60 ns rd 30 1.2t cy + 60 ns delay time from wait remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.) (2/3)
46 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay (3/3) (2) read/write operation (t a = ?0 to +85 c, v dd = 1.8 to 2.7 v) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy 233 ns t add2 (3 + 2n)t cy 240 ns output time from rd 325 ns t rdd2 (3 + 2n)t cy 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 92 ns t rdl2 (2.5 + 2n)t cy 92 ns input time from rd 350 ns t rdwt2 t cy 132 ns input time from wr 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy 60 ns delay time from astb 60 ns delay time from t rdast 0.8t cy 60 1.2t cy ns rd 60 1.2t cy + 120 ns rd 60 1.2t cy + 120 ns delay time from wait remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.)
47 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay (3) serial interface (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck3n... internal clock output) parameter symbol conditions min. typ. max. unit sck3n t kcy1 4.0 v v dd 5.5 v 954 ns cycle time 2.7 v v dd < 4.0 v 1600 ns 3200 ns sck3n high-/ t kh1 , t kl1 v dd = 4.0 to 5.5 v t kcy1 /2 ?50 ns low-level width t kcy1 /2 ?100 ns si3n setup time t sik1 4.0 v v dd 5.5v 100 ns (to sck3n ) 2.7 v v dd < 4.0v 150 ns 300 ns si3n hold time t ksi1 400 ns (from sck3n ) delay time from t kso1 c = 100 pf note 300 ns sck3n to so3n output note c is the load to so3n output capacitance of the sck3n and so3n output lines. (b) 3-wire serial i/o mode (sck3n... external clock input) parameter symbol conditions min. typ. max. unit sck3n 4.0 v v dd 5.5 v 800 ns cycle time 2.7 v v dd < 4.0 v 1600 ns 3200 ns sck3n high-/ t kh2 , t kl2 4.0 v v dd 5.5 v 400 ns low-level width 2.7 v v dd < 4.0 v 800 ns 1600 ns si3n setup time t sik2 100 ns (to sck3n ) si3n hold time t ksi2 400 ns (from sck3n ) delay time from t kso2 c = 100 pf note 300 ns sck3n to so3n output note c is the load capacitance of the so3n output line. remark pd780021a, 780022a, 780023a, 780024a: n = 0, 1 pd780021ay, 780022ay, 780023ay, 780024ay: n = 0 t kcy2
48 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay (c) uart mode (dedicated baud-rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy3 4.0 v (e) uart mode (infrared data transfer mode) parameter symbol conditions min. max. unit transfer rate v dd = 4.0 to 5.5 v 131031 bps bit rate allowable error v dd = 4.0 to 5.5 v note note fbr: specified baud rate
49 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay (f) i 2 c bus mode ( pd780021ay, 780022ay, 780023ay, 780024ay only) parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 kh z bus free time t buf 4.7 1.3 s (between stop and start conditions) hold time note 1 t hd:sta 4.0 0.6 s scl0 clock low-level width t low 4.7 1.3 s scl0 clock high-level width t high 4.0 0.6 s start/restart condition setup time t su:sta 4.7 0.6 s data hold time cbus-compatible master t hd:dat 5.0 s i 2 c bus 0 note 2 0 note 2 0.9 note 3 s data setup time t su:dat 250 100 note 4 ?s sda0 and scl0 signal rise time t r 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto 4.0 0.6 s spike pulse width controlled by input filter t sp ? 0 50ns capacitive load per bus line cb 400 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the undefined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin . of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only the maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in a standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. ?if the device does not extend the scl0 signal low state hold time t su:dat 250 ns ?if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax . + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification). 5. cb: total capacitance per bus line (unit: pf)
50 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay ac timing measurement points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti00, ti01 1/f t5 t tih5 t til5 ti50, ti51 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd
51 data sheet u14042ej3v0ds
52 data sheet u14042ej3v0ds
53 data sheet u14042ej3v0ds
54 data sheet u14042ej3v0ds
55 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay a/d converter characteristics (t a = ?0 to +85 c, v dd = av dd = av ref = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr conversion time t conv 4.0 v av ref 5.5 v 14 96 s 2.7 v av ref < 4.0 v 19 96 s 1.8 v av ref < 2.7 v 28 96 s analog input voltage v ian 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref when a/d converter not operating 20 40 k ? note excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr subsystem clock stop (xt1 = v dd ) and 0.1 30 a supply current feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /fx s time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr
56 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
57 data sheet u14042ej3v0ds
58 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 48 49 32 64 1 17 16 33 64-pin plastic qfp (14x14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.6 0.4 14.0 0.2 0.8 (t.p.) 1.0 j 17.6 0.4 k p64gc-80-ab8-5 c 14.0 0.2 i 0.15 1.8 0.2 l 0.8 0.2 f 1.0 n p q 0.10 2.55 0.1 0.1 0.1 r s 5 5 2.85 max. h 0.37 +0.08 -0.07 m 0.17 +0.08 -0.07 s s n j detail of lead end c d a b r k m l p i s q g f m h
59 data sheet u14042ej3v0ds + ? + ? + ?
60 data sheet u14042ej3v0ds caution do not use different soldering methods together (except for partial heating).
61 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay soldering method soldering conditions wave soldering solder bath temperature: 260 c max., time: 10 seconds max. (only for pins) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. table 14-1. surface mounting type soldering conditions (2/2) (2) pd780021agk- -9et: 64-pin plastic tqfp (12 12) pd780022agk- -9et: 64-pin plastic tqfp (12 12) pd780023agk- -9et: 64-pin plastic tqfp (12 12) pd780024agk- -9et: 64-pin plastic tqfp (12 12) pd780021aygk- -9et: 64-pin plastic tqfp (12 12) pd780022aygk- -9et: 64-pin plastic tqfp (12 12) pd780023aygk- -9et: 64-pin plastic tqfp (12 12) pd780024aygk- -9et: 64-pin plastic tqfp (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). table 14-2. insertion type soldering conditions pd780021acw- : 64-pin plastic sdip (19.05 mm (750)) pd780022acw- : 64-pin plastic sdip (19.05 mm (750)) pd780023acw- : 64-pin plastic sdip (19.05 mm (750)) pd780024acw- : 64-pin plastic sdip (19.05 mm (750)) pd780021aycw- : 64-pin plastic sdip (19.05 mm (750)) pd780022aycw- : 64-pin plastic sdip (19.05 mm (750)) pd780023aycw- : 64-pin plastic sdip (19.05 mm (750)) pd780024aycw- : 64-pin plastic sdip (19.05 mm (750))
62 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay appendix a. development tools the following development tools are available for system development using the pd780024a, 780024ay subseries. also refer to (5) cautions on using development tools. (1) language processing software ra78k0 assembler package common to 78k/0 series cc78k0 c compiler package common to 78k/0 series df780024 device file for pd780024a, 780024ay subseries cc78k0-l c compiler library source file common to 78k/0 series (2) flash memory writing tools flashpro ii (fl-pr2) flash programmer dedicated to microcontrollers with on-chip flash memory flashpro iii (fl-pr3, pg-fp3) fa-64cw adapter for flash memory writing fa-64gc fa-64gk-9et (3) debugging tools ? when using in-circuit emulator ie-78k0-ns ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa performance board to enhance and expand the functions of ie-78k0-ns ie-70000-98-if-c adapter required when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-cd-if-a pc card and interface cable when using notebook pc as host machine (pcmcia socket supported) ie-70000-pc-if-c adapter required when using ibm pc/at tm or compatible as host machine (isa bus supported) ie-70000-pci-if-a adapter required when using pc in which pci bus is incorporated as host machine ie-780034-ns-em1 emulation board to emulate pd780024a, 780024ay subseries np-64cw emulation probe for 64-pin plastic sdip (cw type) np-64gc emulation probe for 64-pin plastic qfp (gc-ab8 type) np-64gc-tq np-64gk emulation probe for 64-pin plastic tqfp (gk-9et type) ev-9200gc-64 conversion socket to connect the np64gc and a target system board on which a 64-pin plastic qfp (gc-ab8 type) can be mounted. tgc-064sap conversion adapter to connect the np-64gc-tq and a target system board on which a 64-pin plastic qfp (gk-ab8 type) can be mounted tgk-064sbp conversion adapter to connect the np-64gk and a target system on which a 64-pin plastic tqfp (gk-9et type) can be mounted id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df780024 device file for pd780024a, 780024ay subseries
63 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay ?when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c adapter required when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at or compatible as host machine (isa bus supported) ie-70000-pci-if-a adapter required when using pc in which pci bus is incorporated as host machine ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-780034-ns-em1 emulation board to emulate pd780024a, 780024ay subseries ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-780034-ns-em1 on ie-78001-r-a ep-78240cw-r emulation probe for 64-pin plastic sdip (cw type) ep-78240gc-r emulation probe for 64-pin plastic qfp (gc-ab8 type) ep-78012gk-r emulation probe for 64-pin plastic tqfp (gk-9et type) ev-9200gc-64 conversion socket to connect the ep-78240gc-r a nd a target system board on which a 64-pin plastic qfp (gc-ab8 type) can be mounted tgk-064sbp conversion adapter to connect the ep-78012gk-r a nd a target system board on which a 64-pin plastic tqfp (gk-9et type) can be mounted id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780024 device file for pd780024a, 780024ay subseries (4) real-time os rx78k0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
64 data sheet u14042ej3v0ds the id78k0-ns, id78k0, and sm78k0 are used in combinaiton with the df780024. the cc78k0 and rx78k0 are used in combination with the ra78k0 and the df780024. fl-pr2, fl-pr3, fa-64cw, fa-64gc, fa-64gk-9et, np-64cw, np-64gc, np-64gc-tq and np-64gk are products made by naito densei machida mfg. co., ltd. (+81-44-822-3813). the tgc-064sap, and tgk-064sbp are products made by tokyo eletech corporation. refer to: daimaru kogyo, ltd. tokyo electronic division (+81-3-3820-7112) osaka electronic division (+81-6-6244-6672) for third-party development tools, see the single-chip microcontroller development tool selection guide (u11069e) . the host machines and oss supporting each software are as follows. host machine pc ews [os] pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k0 id78k0 ? rx78k0
65 data sheet u14042ej3v0ds s manual u14046e s manual instructions u12326e documents related to development tools (user s manuals) document name document no. ra78k0 assembler package operation u11802e assembly language u11801e structured assembly language u11789e cc78k0 c compiler operation u11517e language u11518e ie-78k0-ns in-circuit emulator u13731e ie-780034-ns-em1 emulation board u14642e ep-78240 emulation probe u10332e sm78k0s, sm78k0 system simulator ver.2.10 or later windows operation u14611e based sm78k series system simulator ver.2.10 or later external part user open to be prepared interface specifications id78k0-ns integrated debugger ver.2.00 later windows based operation u14379e id78k0-ns, id78k0s-ns integrated debugger ver.2.20 or later operation u14910e windows based id78k0 integrated debugger windows based reference u11539e guide u11649e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
66 data sheet u14042ej3v0ds pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay documents related to embedded software (user? manuals) document name document no. 78k/0 series real-time os fundamentals u11537e installation u11536e 78k/0 series os mx78k0 fundamental u12257e other related documents document name document no. semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
67 data sheet u14042ej3v0ds
68 data sheet u14042ej3v0ds
69 data sheet u14042ej3v0ds ? ? ? ? ? ?
pd780021a, 780022a, 780023a, 780024a, 780021ay, 780022ay, 780023ay, 780024ay m8e 00. 4 no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is current as of november, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information.

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